1. Field of the Invention
The present invention relates to receivers generally and, more specifically, to calibration of the slicers in the receiver to remove offset errors therein.
2. Description of the Related Art
Communication receivers that recover digital signals must sample an analog waveform and then reliably detect the sampled data. Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. As data rates increase, the receiver must both equalize the channel, to compensate for such corruptions, and detect the encoded signals at increasingly higher clock rates. Decision-feedback equalization (DFE) is a widely used technique for removing intersymbol interference and other noise at high data rates.
Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously detected (or decided) data. In one typical DFE-based receiver implementation, a received analog signal is sliced to generate digital data for further processing. In some high-speed (multi-gigabit) applications, so called “double-rate” receivers with an unrolled digital DFE might be used. However, these receivers are sensitive to offset-induced slicing errors where the slicing threshold determines whether received signal is a one or a zero. Because of circuit imperfections, the slicing threshold may be off by tens of millivolts from a desired value, e.g., zero volts. Because the amplitude of the received signals is around one hundred millivolts, an offset-induced slicing voltage error of tens of millivolts is a relatively large percentage of the signal amplitude and can seriously degrade performance of the overall receiver. It is desirable to quickly and accurately calibrate the slicers to remove or compensate for the offset voltage of the slicer.